1. Field of the Invention
The present invention relates to a reference power supply circuit applied to, for example, a semiconductor device and configured to generate a reference current and reference voltage.
2. Description of the Related Art
A semiconductor device has a reference power supply circuit for generating a reference current and reference voltage. The reference power supply circuit is so configured as to include, for example, a BGR (Band Gap Reference) circuit. In recent years, a power supply of the semiconductor device has been made to have a low voltage and a semiconductor device has been developed which can operate even at a low power supply voltage of below 1.25V (see Japanese Patent Laid Open (KOKAI) No. 11-45125).
FIG. 17 shows one practical form of a conventional reference voltage generation circuit. In FIG. 17, an output voltage PGT of a differential amplify circuit AMP is supplied to the gates of P channel MOS transistors (hereinafter referred to as PMOS transistors P1, P2). This differential amplifier AMP controls the PMOS transistor P1 and P2 so as to make potentials on connection nodes INP and INN equal to each other. At this time, with IA representing a current flowing through a resistor RA; VA, a potential difference across a diode D2; and VA′, a potential difference across resistors RB, RB, the following equation (1) is established:VA′=RA·IA+VA  (1)The current and voltage of the diode are given below.I=Is·exp(q V/kT)  (2)V=V0·ln(I/Is), (V0=kT/q)  (3), noting that Is: reverse saturation current; k: Boltzmman constant; T: absolute temperature; and q: electron charge.
If the equation (1) is modified with the use of the equation (3), then the temperature characteristic of the current IA is represented as follows:IA=V0/RA·ln(ISA/ISB)  (4)Here, ISA, ISB represent the reverse saturation currents of the diodes D2, D1. From the equation (4) the temperature characteristic of the current IA becomesdIA/dT=k/(RA·q)·ln ISA/ISB>0  (5)as shown in equation (5).
Further, the relation between the resistance PB, current IB on one hand and the potential difference VA′ across the resistor RB on the other becomesVA′=RB·IBIB=VA′/RB  (6)as shown in the equation (6).
From the equation (6), the temperature characteristic of the current IB flowing through the resistor RB becomesdIB/dT=1/RB·dVA′/dT<0  (7)
If, at this time, the circuit condition is selected under which the variations of the IA and IB with respect to the temperature cancel each other by their sum as shown in the equation (8) below, then a current supply of a smaller temperature dependence is provided.(dIA/dT)+(dIB/dT)=0  (8)
For example, if the size ratio of the diodes D2, D1 is given by 100:1, then the resistance ratio RB:RA is found as follows:RB/RA=(q/k·dVA′/dT)/ln(ISA/ISB)Here, the numerical value of each parameter is given below.q=1.6e−19 (C), k=1.38e−23 (J/K)dVA′/dT=−2 (mV), ln(ISA/ISB)=ln(100)≈4.6
Therefore, the resistance ratio RB/RA becomesRB/RA≈23/4.6=5  (9)From the equation (9), the resistance ratio RB:RA becomes equal to about 5:1.
If the circuit shown in FIG. 17 is configured with the use of the size ratio of the diodes and resistance ratio above, then the PMOS transistors P1, P2, P3 function as a current supply of a smaller temperature dependence. By connecting a required resistor RC between the PMOS transistor P3 and ground, it is possible to provide an output voltage VREF of a smaller temperature dependence.
By the mismatching (variation) of a transistor pair (not shown) constituting an input stage of the differential amplifier AMP, that of a mirror connected PMOS transistors P1, P2, P3 and that of the characteristics of the diodes and resistors, the output voltage VREF also varies.
Incidentally, in order to make a variation of the above-mentioned output voltage VREF smaller, a method for increasing the size of the resistors RA, RB, diodes D1, D2, transistors P1, P2, P3, etc., and, by doing so, decreasing the variation of each element is taken. Since this method increases the size of the respective elements, a whole circuit size is increased as a first problem and a high manufacturing cost is involved. In particular, the size of the whole circuit is defined by the size of the diode D1 and resistor RB and it is necessary to reduce the size of these.
Further, if the size of the transistor pair constituting an input stage of the differential amplifier AMP is made greater, a parasitic capacitance of a negative feedback circuit is increased and the phase margin is decreased. This poses a second problem of lowering a stability of the circuit involved.
FIG. 18 shows the voltage/current characteristic of the circuit shown in FIG. 17. In FIG. 18, the curve CA′ shows the voltage/current characteristic of a circuit constituting a parallel array of a series-connected resistor RA and diode 2 on one hand and a resistor RB on the other, while the current/voltage characteristic CB′ shows a current/voltage characteristic of a parallel connection array of the diode D1 and resistor RB.
FIGS. 4B and 5B each show an enlarged view of a crosspoint of the two curves CA′, CB′. In the case where the transistor pair constituting an input stage of the differential amplifier AMP has a variation of a threshold voltage, the curves CA′, CB′ are equivalent to the shifted states as indicated by broken lines CA1′, CA2′, CB1′, CB2′ in FIGS. 4B and 5B. At this time, the current values of the PMOS transistors P1, P2 and P3 are shifted to the characteristics of broken lines CIA1′, CIA2′, CIB1′, CIB2′ with respect to an original current value CI′. At this time, the smaller the crossing angle between the curves CA′ and CB′, the greater the variation of an output current value.
In particular, by connecting the resistor in parallel with the diode, the crossing angle between both the curves becomes smaller. As a third problem, this circuit involves a greater variation in output voltage or output current than a circuit not using a parallel connection array of the resistor and diode.
Further, the differential amplifier AMP is generally of a type that an input voltage is applied to the gate of the NMOS transistor pair. In such a differential amplifier, if the temperature rises and the forward voltage of the diode becomes smaller, a source potential on an NMOS transistor pair is lowered and a drain potential on a current controlling NMOS transistor (for example, N3 in FIG. 15) becomes deficient. As a result, if use is made of a differential amplifier of a type that an input voltage is applied to the NMOS transistor pair, there is a risk, as a fourth problem, that a circuit involved will cease to operate under a high temperature condition.
Further, a current additive type reference voltage generation circuit as shown in FIG. 19 has also been developed. Even this circuit involves a similar problem as in the case of the circuit shown in FIG. 17. Further, more circuit elements are required, presenting a problem. There has been an increasing demand that a reference power supply circuit of a compact size be developed which involves less variation in output voltage or output current and ensures a stabler operation.